1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a layout structure of fuses in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same.
2. Brief Description of the Related Art
Numerous semiconductor chips are first fabricated on a semiconductor wafer. The semiconductor chips are tested for proper functionality when they are still regions of the semiconductor wafer on which they are manufactured. In particular, in order to determine whether all the circuit elements of each chip properly operate according to the preset specifications, a variety of tests are performed with various test parameters to determine electrical properties and functions of the chips. If any one of control circuits is found defective in the semiconductor memory chip, it is practically impossible to remove a defect found in the semiconductor memory device. On the contrary, if the defect is found in a memory cell of memory cell arrays, a repair process is performed to replace the defective cell with a redundant memory cell. In other words, if a region of normal memory cells is found defective, a region of spare memory cells, which have previously formed as redundancy cells, can be substituted for the defective region of the normal memory cells, so that the semiconductor memory device can perform normal operations.
In order to remove one or more such defective cells, fuse circuits are provided comprising a plurality of fuses simultaneously fabricated with the memory cells and circuit elements of the semiconductor memory device, as shown in FIG. 1A. The fuses are cut by various conventional techniques such as a laser beam cutting technique, as required, to remove defective cells and to replace them with redundant functional cells.
FIG. 1A illustrates a redundant fuse circuit in a conventional semiconductor memory device, which has been published on Aug. 3 in 1999 and disclosed in U.S. Pat. No. 5,933,382. As show in FIG. 1A, a low redundant fuse circuit consists of a pre-charge transistor 30, a status-maintaining circuit 40, a laser fuse box 50, a pass transistor array 60 and a redundancy signal-generating circuit 70.
In FIG. 1A, the laser fuse box 50 consisting of a plurality of fuses F1, F2 . . . Fn is connected through the redundancy signal generating circuit 70 with control circuits such as decoders of the semiconductor memory device. The control circuits are connected with normal and redundancy memory cells or blocks.
It will be understood that fuse programming has been performed by previously opening or blowing the fuses corresponding to an address of a defective memory cell among fuses F1, F2 . . . Fn in the fuse box 50. According to a fuse programming technique, the redundancy signal-generating circuit 70 activates a signal REDi only when an address corresponding to a defective memory cell is transmitted to address bits of Rai, RaiB, Raj, RajB, . . . Ran, RanB during the normal operations of a semiconductor memory device. Accordingly, in place of the defective memory cell or block, a redundancy memory cell or block is selected to write/read data. The aforementioned fuse programming is a kind of address code cutting process for repairing a defective memory cell or block.
In other words, when a memory cell is found defective, the redundancy fuse circuit, which has been previously fabricated as shown in FIG. 1A, opens a fuse relevant to the address line of the defective memory cell. As a result, a redundancy memory cell is substituted for the defective memory cell.
To fuse, or open a fuse, in the aforementioned fuse box 50 of the conventional semiconductor memory device, there has been provided an electrical fusing method in which a large quantity of current flows for fusing and a laser fusing method in which a laser beam radiates the fuse and thereby opens (xe2x80x9cblowxe2x80x9d) it.
Electrical fusing often has been utilized in the semiconductor memory device such as an Electrical Erasable Programmable Read Only Memory (EEPROM). On the other hand, laser fusing has been utilized primarily in semiconductor memory devices such as a Dynamic Random Access Memory (DRAM).
The fuse box in the redundant fuse circuit typically is configured at a periphery circuit area of a chip. Along with the recent trend of reducing the size of a chip, it is necessary to develop a technique to configure and fabricate the fuse box to occupy as a small area as possible.
FIGS. 1B and 1C illustrate layout structures of a semiconductor memory device in accordance with recent advances. FIG. 1B illustrates a method for fabricating the layout structure of fuses in accordance with the teachings of Korean patent application No. 1998-47293.
As shown in FIG. 1B, laser fuses 111-116 contained in the fuse box 50 of the conventional semiconductor memory device have all the same width W1 and pitch P1. In general, the center region 131 of the laser fuses is where the laser beam is irradiated for fusing. As the size of semiconductor memory chips gets smaller, there should be a reduction in pitch to accommodate the laser fuses 111-116 in the smaller chip. Particularly, as the pitch of the laser fuses gets smaller, other laser fuses adjacent to a particular laser fuse to be cut or blown may be damaged by the fusing (cutting) step. As shown in FIG. 3B, the cross-sectional view taken along line X-Xxe2x80x2 of FIG. 3A, neighboring fuses may have a high probability of being damaged or having electrical shorts therebetween. FIG. 3B illustrates a profile of defects that may practically occur in programming a laser fuse box of a conventional semiconductor memory device.
On the other hand, FIG. 1C illustrates a layout structure of fuses in a laser fuse box of a semiconductor memory device in accordance with a prior art embodiment.
FIG. 1C is a fuse layout disclosed in U.S. Pat. No. 5,747,869 issued May 5, 1998. As shown in FIG. 1C, the laser fuses 151-156 have narrow closely spaced regions 151a-156a and wide space-apart regions 151b-156b. In the aforementioned structure, the fusing process is performed on the fuses 151-153 in wide regions 151b-153b and on the fuses 154xcx9c156 in wide regions 154b-156b so as to reduce the probability of damage to neighboring laser fuses. Although the aforementioned patent shows a laser fuse bank structure that is less susceptible of damaging neighboring fuses, laser fuses may be seen to occupy a large area of the chip due to the width and separation of the laser fuses.
FIG. 2 illustrates the layout structure of fuses in a laser fuse box of a semiconductor memory device in accordance with a further improved prior art embodiment. FIG. 2 illustrates a fuse layout disclosed in Korean Pat. No. 1998-47293. In the layout structure shown in FIG. 2, the empty spaces S1, S2 of FIG. 1C have been eliminated to reduce wasted space and to improve the integration of the laser fuses. However, the regions where fusing is performed in the fuse box shown in FIGS. 1C and 2, are near the top or bottom of the fuses rather than the center region. The width PW of the center region of the fuses is smaller than that of the top or bottom regions of the fuses where fusing occurs. This unfortunately has resulted in a relatively poor condition for fusing. Therefore, it is desirable that the center region of the fuse be protected so as to improve reliability of the product.
As described above, the conventional techniques have focused on the layout structure of fuses in the fuse box to improve integration of the device. However, there has not been sufficient consideration regarding electrical shorts that can be caused by thermal transfer among neighboring fuses. The inventors of the present invention have found new causes to degrade the reliability of the fusing process. The causes can be understood with reference to the accompanying drawing of FIG. 4 and relevant descriptions regarding yet another prior art layout structure.
FIG. 4 illustrates another prior art layout structure of fuses in a laser fuse box of a semiconductor memory device, specifically showing the arrangement of fuses outside the fuse boxes 10, 20.
As shown in FIG. 4, a gap between adjacent fuses is known to be smaller in region B with fuses 11, 12, 21, 22 outside the fuse boxes 10 and 20 than in region A with fuses 21, 22, 23, 24 and than fuses 11, 12, 13, 14 inside the fuse boxes 10 and 20, respectively. The gap is larger in region A than in region B because region A is where a fusing process is performed by a laser beam. When the laser beam irradiates for fusing (blowing) the fuse box shown in FIG. 4, heat is generated and transferred along the layout structure from the inside of the fuse boxes to the outside of the fuse boxes. As shown in FIG. 4, because the gap in region B is smaller, an insulating layer formed between fuses in region B is more vulnerable to the heat generated from the fusing process than the insulating layer formed between fuses in region A. Thus, the insulating layer can be easily destroyed. This causes electrical shorts between neighboring fuses. The electrical shorts between fuses most often occur outside the fuse boxes. But if the gap is sufficiently small within the fuse boxes, then shorts may also occur within the fuse boxes.
Therefore, there is a strong need to develop a technique to improve the layout structure of the fuse box, which preferably would occupy a minimum area in the chip for conveniently performing the fusing process while minimizing influences of the heat generated by fusing neighboring fuses.
Therefore, one object of the present invention is to provide a layout structure of a laser fuse box, which can solve a electrical shorting problem between neighboring fuses in a fusing process, and a method for fabricating the layout structure and for performing a fusing process.
Another object of the present invention is to provide an improved fuse layout structure in a laser fuse box to increase integration degree of a semiconductor integrated circuit and prevent or minimize thermal damage to neighboring fuses.
A further object of the present invention is to provide a fuse layout structure in a fuse box and a method for fabricating the same to occupy a smaller area, but to conveniently perform a fusing process with a minimum thermal influence on the neighboring fuses.
Another object of the present invention is to provide an improved fuse layout structure in a fuse box and a method for fabricating the same, in which a fusing process is selectively performed to laser fuses in a zigzag manner to reduce thermal damage to neighboring fuses.
In order to accomplish the aforementioned objects of the present invention, there is provided a fuse layout structure in a laser fuse box of a semiconductor integrated circuit in accordance with one aspect of the present invention, the structure comprising: a first plurality of conductive fuses each having a straight shape and a predetermined gap therebetween; and a second plurality of conductive fuses each having a vertical run, a bend and a horizontal run, wherein the second plurality of fuses are spaced apart with the first plurality of fuses therebetween.
In accordance with another aspect of the present invention, there is provided a fuse layout structure within a laser fuse box of a semiconductor integrated circuit, comprising: a plurality of neighboring fuses formed with a predetermined gap therebetween to create fuse locations arranged in a staggered configuration, the fuse comprising: a first conductive region extending from one edge of the width of the fuse box to an approximate center line of the fuse box; a second conductive region extending longitudinally from an end of the first region; and a third conductive region extending from an end of the second region to the edge of the fuse box.
In accordance with another aspect of the present invention, there is provided a fuse layout structure in a laser fuse box of a semiconductor integrated circuit comprising:
a plurality of laser fuses formed with a predetermined gap therebetween in the fuse box, the fuses having a central region extending parallel to each other; and
an insulative protection line extending longitudinally within the fuse box to cover the central regions of the fuses and insulating layers formed therebetween to prevent thermal damages to neighboring fuses when a fusing process is selectively performed on the laser fuses in a zigzag manner.
In accordance with another aspect of the present invention, there is provided a method for fabricating a laser fuse box of a semiconductor integrated circuit comprising the steps of: depositing a first insulating layer over a semiconductor substrate having electronic circuit elements thereon; depositing and patterning a silicon layer on a first insulating layer to form a plurality of laser fuses; forming a second insulating layer on the fuses; selectively etching the second insulating layer to a predetermined depth to form windows that define the fuse box; and selectively depositing a third insulating layer in the central regions of the fuses in the windows.
The fuse layout structure in a laser fuse box of a semiconductor integrated circuit in accordance with the present invention is advantageous over prior art fuse layout structure in that it occupies a smaller area. And the fuse layout structure of the present invention allows a fusing process to be performed easily and prevents or minimizes thermal damage to neighboring fuses during the fusing process. Therefore, the probability of electrical shorts between fuses can be minimized and reliability of repairing processes can be improved.